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Quad SPI-3 to SPI-4 Link Layer
Lattice Semiconductor
Table 3. Register Map for Quad SPI-3 to SPI-4 LINK Layer Bridge Core
Bridge Core User’s Guide
Address: 0x8000
Name: ID/Version Register
D7
D6
D5
D4
D3
D2
D1
D0
ID/VER
Default value: 0x01
Description:
ID/VER
Address: 0x8001
Mode: Read Only
The ID and version number of this core.
Name: Parity Control Register
D7
D6
D5
D4
D3
D2
D1
D0
—
—
—
RX_PAR
TX_PAR
Default value: 0x03
Description:
TX_PAR
RX_PAR
Address: 0x8002
Mode: Read/Write
When high, odd parity is supported on the SPI-3 transmit interfaces.
When high, odd parity is supported on the SPI-3 receive interfaces.
Name: Transmit Parity Error Register
D7
—
D6
D5
—
D4
D3
PERR_3
D2
PERR_2
D1
PERR_1
D0
PERR_0
Default value: n/a
Description:
PERR_N
Address: 0x8003
Mode: Clear on Read
Detection of a parity error on any port on interface N sets this bit. This bit clears upon reading.
Name: DPRAM Read Provisioning Register 0
D7
D6
D5
D4
D3
D2
D1
D0
—
—
RSEL_0
Default value: Depends on con?guration. See Functional
Description section.
Description:
Mode: Read/Write
RSEL_0
Address: 0x8004
Selects virtual FIFO to be read during cycle 1 of 8.
Name: DPRAM Read Provisioning Register 1
D7
D6
D5
D4
D3
D2
D1
D0
—
—
RSEL_1
Default value: Depends on con?guration. See Functional
Description section.
Description:
Mode: Read/Write
RSEL_1
Selects virtual FIFO to be read during cycle 2 of 8.
7
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